Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems

Fault-tolerant floating-point multipliers are essential for mission-critical systems to avoid faults caused by radiation. The primary issue is the hardware overhead of these circuits. It also leads to higher power consumption. To overcome these issues, we are proposing a preferential fault-tolerant floating-point multiplier. The proposed multiplier architecture was designed using an error-analysis approach. This design will mitigate the faults and also reduce the hardware cost of utilization. The proposed work was analyzed with single precision floating point multipliers. The performance and efficiency of the proposed work were analyzed by simulation and implemented on the FPGA.