Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis

In this paper, we propose a IT DRAM with an electrostatic barrier to improve the retention time of the device. The proposed device utilizes a misaligned double-gate to store holes and distinguish between the two logic states 0 and 1. We optimize the work function of the back gate and front gate to obtain the requisite concentration profiles in an intrinsic silicon body. Further, we introduce an electrostatic barrier using back gate extensions and have carried out work function engineering to improve the retention time. The electrostatic barrier significantly suppresses the recombination rate of holes under the back gate. Consequently, it improves the retention time by $\sim 500\times$ compared to the device with no such barrier, accompanied by some reduction in the sense margin.