MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy

As technology advancement continues beyond the sub-10 nm process node, modern high-frequency designs are more prone to damage due to electrostatic discharge (ESD) effects. Protecting a device from an ESD event is one of the major reliability aspects of any modern SoC implementation. The current industry practice is to place the ESD clamp cells in the design and connect them with the power and ground bumps using a lower resistance such that most of the transient current will pass through the low-resistance path. To ensure the ESD resistance is lesser than the resistance through the logic cell, designers used to perform a time-intensive ESD simulation after every design modification with respect to the ESD requirements in industry-standard EDA tools, which delays the overall ESD convergence process. In order to address this problem, Machine Learning (ML) techniques are adopted in this research to reduce the number of simulation cycles. Relevant features are identified, and a number of regression algorithms are explored for ML training. The XGBOOST regressor is selected as the best trained model. On the inference dataset, predicted ESD resistance has a very good correlation $\left(R_{{score}}^{2}\gt 0.99\right)$ with the sign-off accurate simulation result. With the fast and almost accurate prediction of ESD resistance, designers can now opt for the detailed simulation intermittently over the ESD convergence process based on time availability. This can lead to more than two weeks of left-shift in the ESD convergence process.