Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive

True Random Number Generators (TRNGs) are crucial components in hardware-entangled cryptography. These modules are effectively used for key generation, initialization vector generation, random simulations etc. The importance of hardware security urges us to develop a compact and scalable hardware security primitive such as TRNG, which can be an integrated module in Integrated Circuits (ICs). This work aims to design and prototype a non-identical Ring Oscillator (RO) based TRNG whose structure is modified using Programmable Delay Line (PDL) inverters. A 3-bit PDL inverter structure has been employed in this work. Hence, these inverters have three different delay control options through which the propagation delay of the inverters is controlled in eight possible ways. Jitters from the RO are disturbed using these delay controls, which increase the standard deviation of the jitters. This phenomenon produces high-quality true random bits. The design was developed using VHDL and implemented on Cyclone IV E Field Programmable Gate Array (FPGA). The true randomness was confirmed through restart experiments and autocorrelation. The average entropy of the true random bits is calculated as 0.999999, which is close to ideality. Further, random characteristics of RO TRNG have been verified through NIST SP 800 – 22 batteries of tests. This TRNG design occupies only <1% of the total hardware elements of the target FPGA and dissipates 147.97 mW of power to generate 2 million bits at 24Mbps throughput.