Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits

In this paper, a new ring amplifier architecture is proposed. The new architecture uses a parallel-series diode-connected resistor in place of a resistor in the second stage of the conventional self-biased ring amplifier. The settling time, dead zone voltage, and output voltage of the ring amplifier all are improved to a great extent. The proposed modification is implemented and verified using simulations in Cadence Virtuoso with 45nm industry standard CMOS technology. The simulation results demonstrate that the modified ring amplifier achieves a settling time of 3.51 ns and the dead zone voltage is 998.60 mV which is $0.54 \times$ and $1.21 \times$ than that of the conventional self-biased ring amplifier. 2000 Monte Carlo simulations on settling time show the proposed circuit is robust against the process variations and has minimum deviation.