Evaluation Trends and Development In Integrated Circuit Parasitic Extraction

With the advancement in circuit performance (higher speeds) and density increase (Moore’s law) in deep sub micrometer (DSM) designs, interconnect parasitic effects become more and more important. Accurate parasitic extraction during IC design is mostly required as feature sizes shrink, process technologies become more complex, and the design margin gets smaller. This paper looks at the current state and trends of parasitic extraction for resistance and capacitance. Evaluation trends along with case study of machine learning based parasitic extraction method is presented in this paper and a fairly comprehensive list of references is provided.