Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique

Circuits for a 1-bit complete adder are proposed in this paper. The suggested circuits have very low power consumption and minimal delay [1]. CMOS technology is used to develop various complete adder circuits with low power consumption and minimal delay. Cadence Virtuoso at 90nm technology is used to implement these, with a 1.8V supply voltage. The power consumption [2], delay, and area parametric restrictions are compared with various complete adder circuit designs, and comments are made on which design provides the best performance parameter. The Power Delay Product indicates the circuit’s efficiency. Since the primary focus of VLSI research is low power design, create circuits with low power, little area, and little latency. The whole adder circuit design performance is related to the complete design performance.