Design and Implementation of High Throughput and Efficient FIR Filter Architectures Using Pipelining

A methodology to improve throughput and efficiency of FIR (Finite Impulse Response) filter architectures by using pipelining is addressed in this paper. Low pass FIR filter of broadcast type structure of 11 tap is designed to improve throughput and efficiency. Feed-Forward Cutset pipelining method is used to pipeline proposed low pass FIR filter architectures. 16 bit RCA (Ripple Carry Adder) and 8*8 bit vedic multiplier is used to do addition and multiplication operations of the proposed FIR filter architectures. VHDL (VHSIC Hardware Description Language) language and Xilinx Vivado 2015.2 tool are used to design, simulation and synthesis. There is an improvement of 50% in area utilization (in terms of Look up Tables) for the implemented 11 tap broadcast FIR filter architectures in comparison with existing 2-tap and 3-tap FIR filter architectures. Also an improvement of 46% in speed for the implemented 11 tap broadcast FIR filter architectures in comparison with existing 2-tap, 3-tap and 4-tap FIR filter architectures.