A Novel Operating Condition Simulation Test Circuit Topology for Saturable Reactors in UHVDC Converter Valves

Existing converter valve testing methods cannot fully simulate the impact of the turn-on and turn-off of single valves of other bridge arms belonging to the same six-pulse converter. The voltages caused by the turn-on and turn-off processes of the converter valve are different, and existing testing methods cannot provide such voltage waveforms. To solve these two problems, this paper proposes a saturable reactor test circuit topology and a control sequence. A saturable reactor operating condition simulation test platform is established. The simulation and experimental results indicate the effectiveness of the proposed test circuit topology and testing method.