A Low-Power Modified Strong-ARM Latch-Based Comparator for Biomedical Applications in 130nm CMOS Technology

SAR ADC comparators occupy 50%-60% of the total energy consumption, even with advanced technology and lower supply voltages. Comparator design represents a critical challenge in achieving a rail-to-rail input range while maintaining low power consumption specially in biomedically utilized SAR ADCs. This paper focuses on enhancing the performance of the Strong-ARM (SARM) Latch-based comparator through innovative modifications to its two preamplifier stages which are integrated to effectively eliminate the DC offset voltage and mitigate the kickback noise. The proposed circuits benefit the Gm/ID methodology while operating in weak inversion for reduced power SAR ADCs. According to obtained post-layout simulation results, the SARM Latch-based comparator consumes only 18.9nW from a 0.65V power supply.