A 6-GHz 78-fs $_{\mathrm{RMS}}$ Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving $-$ 92-dBc Reference Spur and $-$ 258-dB FOM

A double-sampling phase-locked loop (DSPLL) with low jitter, low spur, and low power is presented. It uses low-ripple bootstrapped double-sampling phase detectors (DSPDs) to lower the PD’s in-band phase noise (PN) by about 4 dB without compromising the phase-locked loops (PLLs) spur level and power efficiency. A low-noise multimodulus divider (MMD) is proposed to avoid the use of power-hungry retimers after it, further improving the jitter-power figure of merit (FOM). With a 100-MHz input sinewave reference, the prototype in 28-nm CMOS achieves an rms jitter of 78 fs integrated from 1 k to 100 MHz, a spur level of
$-$
92 dBc with an FOM of
$-$
258 dB. The total power consumption is 2.6 mW at 6 GHz and the active area is 0.2 mm
$^{{2}}$
.