Analytical Model of SRAM VMin to Predict Reliability and Process Impact

SRAM minimum operating voltage (VMin) is statistically distributed and limited by the failure mechanisms of the bitcell & the memory periphery. We propose a Machine Learning based predictive modeling framework for SRAM VMin to estimate the impact of Reliability and process variations. The analytical approach leverages the SPICE model's accuracy and enables accurate prediction of memory VMin before the availability of exhaustive Silicon results. The study is being demonstrated with silicon results and validated on a single port high-density memory bitcell.