Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures

This paper provides an in-depth discussion of hardware magnitude comparators and their implementations for use in System on Chip designs as well as presents a novel design that iterates on existing implementations. Although magnitude comparators are common, designs seldom focus on this important functional unit, sometimes choosing to reuse existing hardware at reduced efficienty. Additionally, the proliferation of heterogenous computing for high performance applications has re-opened a need for ASIC- and FPGA-ready functional units, like comparators, to accelerated workloads varying from database maintenance to graph analytics. We present results that show a significant improvement over synthesis-generated comparators using both prefix adders and tree-based implementations. The results are given in TSMC 28hpc+ 28nm technology using ARM-based standard-cells and commercial EDA toolsets.