TOSA: Tolerating Stuck-At-Faults in Edge-based RRAM Inference Accelerators

Applications powered by Deep Neural Networks (DNNs) are shifting from cloud to edge computing due to the promising performance efficiency of Resistive Random Access Memory (RRAM) devices. However, modern RRAM devices have various possible faults, including hard and soft faults. Existing RRAM-based deep learning systems lack a comprehensive fault tolerance approach, leading to safety risks in deploying edge-end DNN inference. In this paper, we propose an effective fault recovery framework called TOSA to safeguard edge-based DNN accelerators from Stuck-At-Faults (SAFs). Two novel ideas are presented to enhance reliability in edge-based RRAM inference accelerators: (1) SAFs-aware priority-based bit-memristor mapping algorithm to match integrated SAF variations and DNN’s defect tolerance, (2) a new retraining method called joint retraining to recover model accuracy from multiple faulty edge devices. We thoroughly evaluate TOSA on multiple DNN models, demonstrating its effectiveness in reducing costs and improving efficiencies. Experimental results show that TOSA achieves a 45.28× speedup when compared to the per-device retraining methods while preserving inference accuracy better than the latest competitor, making it a reliable architecture for accelerating DNN inference on edge devices.