Accelerating SAT Solving Using Switching ASICs

People have been leveraging the capabilities of programmable switches, which are programmable in the data plane and process packets at the line rate, to improve the performance of distributed systems. However, few have explored whether programmable switches can speed up problem-solving. In this paper, we select the SAT problem, one of the most fundamental problems in computer science, as a case study to first explore the feasibility and benefits of this line of research. Our intuition is that by exploiting the parallel lookup capability of programmable switches, we can substantially speed up the process of checking whether an assignment is a solution to a SAT problem. Consequently, we design conflict tables using TCAM to quickly check assignment satisfiability. Building on the conflict tables, we propose two SAT solvers, P4-DPLL and Antler. Specifically, P4-DPLL is based on the classical DPLL algorithm and implements a stack data structure using registers and SRAM to efficiently make variable search decisions in the data plane, while Antler utilizes the mirroring capability of the programmable switch to further accelerate the SAT solving, which improves the non-parallel depth-first search-based P4-DPLL into a parallel breadth-first search-based SAT solver. We implement the prototypes of P4-DPLL and Antler on the Tofino switch, and evaluate their performance extensively. Results show that P4-DPLL and Antler improve the solving time by 2x and 169x on 90% quantile of test cases, compared to a CPU-based DPLL implementation. Besides, compared with the most popular SAT solvers, MathSAT and Z3, Antler improves the solving time by 42x and 35x, respectively.