An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks

This brief presents the implementation of a 6T SRAM-based array that computes matrix vector multiplication in binarized neural networks. A 6T SRAM bitcell with PMOS access transistors is proposed, which mitigates the read disturb issue that is attributed to the conventional 6T-SRAM bitcell. The degradation in classification accuracy is minimized by the lower mobility of PMOS access devices and by connecting custom Metal-Oxide-Metal capacitors to the bitlines in compute-mode. A single slope ADC is also proposed that enables the macro to compute partial multiply and accumulate value with 5b output precision. The estimated inference accuracy on MNIST and CIFAR-10 datasets is 96.5% and 87.2%, respectively. The macro consumes 1.01 (6.30) fJ of energy per operation to compute 1b-MAC (5b-MAC), and thus achieves a simulated energy efficiency of 984 (157.6) TOPS/W and a compute density of 242 (15.16) TOPS/mm2 at 370MHz in a TSMC 65nm LP CMOS process.