Hardware Implementation of Shadow Lightweight Block Cipher for Resource-Constrained IoT Devices

The development of the Internet of Things has led to a notable increase in the adoption of low-power, multipurpose sensors. Ensuring data security during transmission is crucial for these Internet of Things nodes. A compromised node can severely damage the network. However, due to their limited resources, it is difficult to implement suitable cryptographic functionality on constrained devices. In such circumstances, lightweight cryptography acts as a benefactor. A lightweight cryptographic method is a protocol that is intended to be used in situations with limitations, such as RFID tags, contactless smart cards, sensors, etc. Because of the peculiarities of rotation, XOR (ARX), and addition or AND operations, the round function must be based on the Feistel structure in order for decryption to be accurately performed. The issue with ARX-based block ciphers is that they only modify half of the plaintext block at a time, requiring additional rounds of iteration. In this project, a new logical approach that combines generalized Feistel structure and ARX operations is implemented. The challenge faced by conventional ARX ciphers is that they can only spread half of a plaintext block in a single round. Shadow solves this issue by considering the complete plaintext block. In order to guarantee the effectiveness of the encryption hardware circuit while preserving the security of the physical-layer signal, the suggested study examined the round-based hardware design of the Shadow cipher. The use of VLSI technology in the form of Xilinx software is also done in the paper. Shadow has shown almost 3 times better efficiency as compared to other block cipher.