A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling

This brief presents a 24 Gb/s NRZ receiver. To achieve an energy-efficient receiver, duobinary sampling with half-baud-rate operation is proposed. The duobinary sampling reduces the power consumption of an analog front-end (AFE) by reducing the required bandwidth of the AFE from conventional NRZ Nyquist frequency,
$f_{\mathrm { b}}$
/2, to
$f_{\mathrm { b}}$
/3. The two decoding blocks operate at a half-baud-rate using only a 6 GHz differential clock. Therefore, additional clocking power for the four-phase generation and distribution is saved. The prototype chip was fabricated in a 28 nm CMOS process and occupied an active area of 0.0021mm2. The data rate of 24 Gb/s is achieved with a channel loss of 17.1 dB at 12 GHz. The power consumption was measured to be 10.8 mW, exhibiting an energy efficiency of 0.45 pJ/b.