TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design

The standard-cell methodology is widely adopted in the VLSI design flow due to its scalability, reusability, and compatibility with electronic design automation (EDA) tools. However, the fixed positions and confinement of PMOS and NMOS transistors within its standard cell layout impose limitations on overall wirelength and area optimization. Directly placing individual transistors in a design can provide greater flexibility to explore more diffusion-sharing opportunities, which can potentially result in less wirelength and areas than standard-cell-based designs. Unfortunately, existing transistor placement approaches are limited to a very small scale, e.g., a single standard cell. This paper presents TransPlace, the first transistor-level placement framework that is capable of handling a large number of transistors while considering the overall diffusion sharing and wirelength optimization. Experimental results demonstrate its effectiveness in minimizing wirelength and reducing design area beyond the limits of standard-cell-based designs.