Memory-Centric Microcontroller (MCU) Architecture Design and Implementation

The traditional microcontroller (MCU) architectures generally rely on the CPU as the central processing unit, which often becomes a bottleneck for overall system efficiency. This paper presents a novel approach known as the memory-centric MCU architecture, along with a data transmission method. In Mem-MCU architecture, the CPU, memory, and peripherals share a common bus ring. The CPU and peripherals act as bus master devices, accessing the SRAM through the bus ring. All bus master devices are mapped to device control block data structures in the memory SRAM. After configuring the device control blocks through software, each bus master device can operate concurrently and automatically, facilitating data transfer between the bus master devices and the memory SRAM. Design and simulation results demonstrate that this method reduces chip costs, conserves CPU resources, and improves data transfer efficiency. Additionally, it enhances convenience, abstraction, and flexibility in software development.