A 0.5–2.5 GHz Mixer First Receiver With 200 MHz RF Bandwidth and +18.5 dBm OB-IIP3 in 180 nm CMOS for 5G NR Band

This article presents a novel fully differential four-path passive mixer first receiver architecture, offering a wide radio frequency (RF) bandwidth and improved out-of-band (OOB) rejection. The design utilizes a current reuse approach in the process voltage temperature (PVT) resistant complementary transimpedance amplifier (TIA) to achieve excellent noise performance while minimizing power consumption. Besides, the integration of a second-order Twin-T Elliptic Low-pass Notch filter (TTE-LPNF) followed by the TIA enhances the linearity performance of the receiver and helps achieve wideband response due to positive capacitive feedback and shunting notch. The active RC-based buffer circuit is designed to efficiently drive a
$50~\Omega $
load impedance while providing substantial bandwidth. Moreover, the paper proposed a novel clock generator architecture based on a passive polyphase filter (PPF) and digital combinational logic that has reduced the required input local oscillator (LO) frequency by half compared to the conventional architecture for the same LO output, therefore, reducing the clock power. As a proof of concept, the proposed receiver is fabricated in TSMC 180 nm CMOS technology, and measurement is performed in the lab at room temperature. The receiver demonstrates an impressive RF bandwidth of 200 MHz while operating smoothly within the frequency range of 0.5 - 2.5 GHz. The proposed mixer first receiver has achieved a conversion gain of 29 dB, a noise figure (NF) of 5.8 dB at the LO frequency of 1 GHz, and an out-of-band third-order intercept point (OOB-IIP3) of +18.5 dBm with power dissipation of 27 mW in signal path and 34 mW in clock path while operating at 1.8 V.