FPGA Design of Iterative Messaging Algorithm based on Pseudo Code Capture

Pseudo code capture plays an important role in intelligent FPGA design, but there is a problem of inaccurate fault location. Traditional swarm capture algorithms cannot solve the logic gates and configurable interconnect networks in smart FPGA designs, and the computational effect is not ideal. Therefore, this paper proposes pseudo code capture based on iterative messaging algorithm and analyzes logic gates and configurable interconnection networks. Firstly, the methods of probability graph model theory and graph theory is used to locate the influencing factors, and the indicators is divided according to the requirements of pseudo code capture to reduce the interference factors in pseudo code capture. Then, the FPGA pseudo code capture scheme of iterative messaging algorithm is formed by using the methods of probability graph model theory and graph theory, and the pseudo code capture results is comprehensively analyzed. The MATLAB simulation results show that under certain evaluation criteria, the iterative messaging algorithm is superior to the traditional bee colony capture algorithm in terms of pseudo code capture accuracy and pseudo code capture influencing factor time.