A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing

VLSI architectures play a vital role in most real-time applications because of their optimal performance. In this work, a single MAC (Multiply-Accumulate) based pipelined architecture is proposed for faster computation of the one-dimension (1-D) discrete wavelet transform (DWT). The main objective of this work is to reduce computational complexity by utilizing resource sharing and to enhance the speed of operation by employing a pipelining scheme. The designed single MAC-based architecture for computing DWT is suitable for infrasound data processing which employs a high-pass filter (HPF) and low-pass filter (LPF). The architecture efficiently implements a resource-sharing scheme by adopting only these two filters. In addition, in this realization, pipelining is utilized to achieve high-speed computation of DWT. Further, this design makes use of common elements several times which provide a convenient and suitable implementation. The proposed structure is coded using Verilog and implemented in FPGA (Field Programmable Gate Array) hardware with the Xilinx platform. Intending easily transported and real-time utilization, this architecture is realized using Xilinx Virtex-5 series FPGA. The area of the proposed architecture is reduced by about 44.8% when examining conventional parallel MAC architecture. Likewise, this pipelined design offers power conservation of about 31.97% over the parallel design. Further, the proposed architecture offers an operating speed of 276MHz with a power conservation of 200mW at 276MHz clock frequency.