Design of Capacitive Digital Isolation Chip

Isolation refers to the physical isolation of a circuit through transformers, capacitors, and optocouplers, which can prevent DC and harmful AC currents from passing between two parts of the system, but allows for signal and power transmission. By adopting a gate capacitor scheme that can be integrated into standard CMOS processes, compared to using transformers or optocouplers as integrators and traditional discrete device isolation circuits, capacitive isolation can greatly reduce the volume occupied and facilitate miniaturization of related applications. This article proposes a capacitive digital isolator scheme, which achieves good characteristics of blocking interference transmission during digital signal transmission through OOK modulation and FSK demodulation. The specific circuit design is carried out using the Huahong BCD350GE process, which mainly includes two modules: transmitter TX and receiver, and is simulated and verified through Cadence Virtuoso. The simulation results show that the isolation chip can operate normally within the power supply range of 3.3-5V, with a temperature range of −40°C-120°C, a maximum data transmission rate of 25Mbps, a delay of 20.82ns, and a pulse width distortion of 10.11ns. Under a l5pF capacitive load and 5V power supply, the maximum power consumption is l8.91mW.