FPGA Architecture for High-speed TCAM-based Packet Parsing

Packet parsing is the first and foremost step, it is a pivotal function due to the high level of dependencies on the process of parsing concerning the field extraction. Therefore, the parser needs to eliminate possible latencies and yet retain the efficiency of the parser block. Normally, Ternary Content Addressable Memories (TCAMs) are used to perform high-speed lookup operations. TCAMs intakes input word and search for the most matching data from the static random-access memory (SRAM) and returns the address of the matched data within a single clock cycle. New packet protocols can be updated swiftly with the use of TCAM by simply updating the look-up-tables (LUTs) and some rudimentary changes in the parse graph and thus the parsing algorithm. This paper presents an efficient multi-pumping enabled TCAM-based parser for faster yet efficient packet parsing with improved flexibility of the parser. The multi-pumping technique in memory units internally clocks the dual-port SRAM block at an integral multiple of the external system clock. In this way, the TCAM can retrieve the essential information from the SRAM within one cycle of the external clock as a reference. In this architecture, the TCAM block is divided into multiple sub-blocks of the configured dual-port block RAM (BRAM) and is clocked at an internal frequency which is P times the frequency of the external clock, where P is the multi-pumping factor or the number of sub-blocks of the TCAM. By implementing this methodology, a minimum number of sub-blocks are accessed per search instead of searching the whole TCAM in parallel, which is not energy efficient and is relatively slower than the implemented method. Compared to the existing TCAM-based parser, in this work, the solution achieves about 2.5 to 3 times improved performance in terms of speed.