Design and analysis of Low Power Current Starved Voltage Controlled Oscillator using Reverse Body Bias in 90nm CMOS Technology

This paper presents a low power current starved voltage-controlled oscillator (CSVCO) with five-stages and reverse body bias technique. The design is simulated on 90nm CMOS technology. Modified CSVCO with reverse body bias is showing the phase noise of -70.868 dBc/Hz with an offset frequency of 1 MHz. Modified VCO works in the frequency range of 4.086-3.927 GHz. The proposed VCO shows low power consumption of 55.07-49.74 µW. Compared to other VCO modified circuits shows 8.874 % decrement in power consumption.