A charge-balancing voltage-to-frequency converter in a 180 nm CMOS process

This paper presents a highly accurate temperature-compensated charge-balancing voltage-to-frequency converter designed in a 180 nm CMOS process. The output frequency of our circuit varies over a range of 2 MHz for an (negative) input range of 3.3 V. The circuit exhibits less than 0.016% nonlinearity error while consuming a power of 2mW. The output frequency of our circuit exhibits a variation of 220 ppm over $0-100^{\circ}\mathrm{C}$ after minimizing the temperature coefficient of the resistors used. The sensitivity of the VFC can be varied by changing the clock frequency of the comparator and a reference current.