Power Integrity Design of Mobile 3D-IC Based on the Allocation of Optimal Number of TSV, BGA, and Via

In this paper, the power integrity (PI) optimization design method is presented by utilizing the genetic algorithm (GA) to allocate the optimal number of through-silicon via (TSV), PKG via, ball grid array (BGA), and board via for 3D-IC. The system-level power distribution network (PDN) environment for 3D-IC is established based on the physical modeling method. The proposed optimal design method provided design results that are unbiased toward specific power domains compared to the random search. Through the PI analysis based on the optimized results, valuable insight can be obtained for the practical design of 3D-IC.