Design and Optimization of a Low-Power Comparator for a 10-Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for General-Purpose Applications

Analog-to-digital converters play a pivotal role in signal processing, especially in applications demanding low power consumption and extended battery life. Among the various ADC architectures, the Successive Approximation Register (SAR) ADC is particularly effective for applications requiring low power, moderate resolution, and moderate speed. In this study, we present an enhanced design of a dynamic latch comparator that maintains area efficiency while significantly reducing power consumption. The modified dynamic latch-based comparator was meticulously designed and simulated using LTSpice, resulting in a circuit that consumes less power. This comparator consists of two distinct stages: a dynamic differential input gain stage and an output latch. The suggested circuit was implemented using a 180 nm standard technology and optimized for SAR-ADCs operating at a 5V supply voltage. Our enhanced design strikes a balance between area efficiency and power efficiency, making it an ideal choice for low-power applications.