Implementation of a 32-bit MAC unit in AISC flow using Vedic Multiplier and CSA

This paper majorly focuses on the developing an IP i.e., a 32-bit MAC in Verilog HDL using Vedic multiplier along with CSA and implementation of design using ASIC flow. This is a combinational circuit designed through a hierarchical approach, promoting modular and scalable architectures, reducing redesigns and integration time. An ancient Vedic principles-based Multiplier is used with a Carry Save Adder which will reduce the complexities to keep the design simpler and efficient. The simulation of the MAC unit is performed in Cadence Xcelium. The key differentiator of this unit is that it is implemented using ASIC flow on Cadence tools like Genus and Innovus which is the physical design process using the technology library of 45nm. There is an effective execution of floor planning which is crucial to minimize the physical layout's overall area and optimal use of power. There was detailed analysis conducted to obtain better results on the previously published similar designs. In the physical design implementation process the MAC unit is synthesized and floorplanning is performed along with placement of the design. Further routing is performed to ensure physical connections between the gates are created while minimizing total wirelength, meeting timing requirements, and avoiding violations of design rules.