Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator

The hardware accelerators are essential for high-performance and energy-efficient implementation of machine learning algorithms in hardware. The multiply-and-accumulate (MAC) operation is the fundamental operation in the machine learning algorithm. In this work, we proposed an in-memory computation architecture using a 6T SRAM array along with a specialized delay cell in which the multiplication operation of the MAC is performed in the voltage domain, and the accumulation operation of the MAC is performed in the time domain. The proposed delay cells can be cascaded to form a ring oscillator (RO), which converts the value of the MAC to the frequency of the RO. A simple digital counter is sufficient to measure the frequency of the RO. The counter occupies less area than the analog-to-digital converter (ADC), needed for voltage-domain-based IMC, and the time-to-digital converter (TDC), needed for time-domain-based IMC. The simulation of the proposed architecture in an industrial 65 nm process achieves 10.32/1321.2 GOPS, 30.3149.5 TOPSIW energy for serial/parallel access of rows, and 99% classification accuracy on the MNIST images.