Design of Low Power ALU for RISC-VISA

RISC-V, an open and versatile Instruction Set Architecture (ISA), offers numerous enhancements and serves as a flexible foundation for incorporating optional additions that facilitate the development of general-purpose software. Processor designers primarily aim to enhance power efficiency and reduce latency in their designs. Arithmetic and Logic Unit (ALU) unit being the element of the processor consuming more computational power becomes the target of our work. In our design, we adopted the open-source RISC-VISA standard and redesigned the ALU unit of the processor for better power efficiency. In this research, we have successfully implemented a unique latch-based ALU architecture that demonstrates improved resource utilization. By strategically incorporating latches, we have effectively enabled the computational blocks specific to the desired operation, resulting in enhanced efficiency. The entire design is implemented using traditional Verilog. The design has been synthesized in the Cadence Genus synthesis platform using 90nm technology. Our work has shown a significant reduction of 9.44 % in the total power consumption.