Design and Performance Analysis of Dynamic and Hybrid CMOS Threshold Logic Based Full Adder Circuit

Researchers have proposed various CMOS based full adder circuits. Here a new hybrid CMOS TLG design of full adder is presented using Ganged CMOS and COWL (Capacitive output wired Logic) based Threshold Logic Gate. Full adder circuit has been also designed here using two dynamic CMOS based TLG. One is dynamic capacitive output wired logic and another one is CMOS capacitor coupling logic (C3L). The performance parameters of the various TLG based full adder circuits were compared and the hybrid CMOS TLG based full adder circuit showed the best performance.