A hardware implementation of genetic algorithms for measurement characterization

To process/store/analyze signals acquired from sensors, hybrid systems with flexible and adaptable intelligent information processing and perception (IIPP) are needed. Genetic algorithms (GA) present a suitable pre-processing operation because of their good convergence to optimum solutions and characterization capabilities. Most GAs are built via software because of their ease of editing and customization. Less attention has been given to hardware implementation of such algorithms. We present a hardware design approach of a GA for optimum measurement representation/characterization to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new time efficient approach for crossover based on preassigned least error value is proposed. The crossover scheme is called half siblings and a clone. Such a scheme needs 10 iterations to converge the system proposed for sensor measurement characterization. This takes 7680 clock cycles, which is only 96 /spl mu/sec when implemented in the 0.25 /spl mu/m CMOS technology.