Analysis of power combiner architecture for push-pull transistors with on-chip and on-board coupling

Push-pull transistor consists of two dies on common package. It offers advantage in space, cost and process invariance between dies. However, on-chip and PCB layout RF coupling between branches of push-pull transistors becomes unavoidable. In such scenario with significant coupling, an amplitude imbalance is created. When coupling in push-pull amplifier is analyzed, it is analytically deduced that amplitude imbalance is maximized with quadrature splitter and is minimized with in-phase or out-of-phase splitter. The theoretical formulation is validated by simulation and is confirmed by measurements on practical prototype. Two amplifiers are designed using a push-pull transistor with significant on-chip and PCB layout coupling. In one of the amplifiers with quadrature hybrids, power imbalance resulted in imbalance in power dissipated in each die and created asymmetry in junction temperature of the dies resulting in reduced power delivery of amplifier. However, the amplifier with 180° splitter could maintain amplitude balance and deliver designed power of 53dBm. A power amplifier has been designed according to this design methodology and integrated into a SSPA module. The module can operate in CW mode at 200W across 2.5-2.7GHz.