SOI SRAM design advances & considerations

SOI is a relatively new introduction in memory design and its use can improve performance. Bit-line capacitance and pass gate loads are major sources of current discharge in SOI SRAM cells. Currents from bit line capacitance and cell leakage can corrupt the cell data. SOI improves the soft error rate due to Alpha particles, mainly because of the presence of buried oxide. This paper is a brief tutorial on SOI SRAM design issues, leakages and soft error rates.