A Parallel Read-Write Circuit Design for Driving Memristor Crossbar Array

Memristor crossbar array is considered as a promising circuit module for accelerating neural networks. Because the memristor is tunable and multi-state, it is important to design applicable Read-Write (RW) circuit for driving memristor crossbar array. In this paper, a novel RW circuit based on analog circuits is proposed for tuning memristors in high-dimensional array parallelly, which is scalable and low-overhead. The standalone RW circuit schematic is presented for reading/writing single memristor and verified in circuit simulation. Then, we extend and apply this circuit into a two-dimensional memristor crossbar array. The performance of memristor crossbar array controlled by designed RW circuits is verified via the simulations under various machine learning datasets. The comparison with related works is presented, which demonstrates the advantages of the proposed RW circuit regarding overhead and anti-error.