High-speed GaAs SCFL digital test structures

The work presented in this paper describes the simulations performed in order to evaluate expected performance of digital cells processed in 0.5-/spl mu/m GaAs MESFET technology, before these cells are measured on-chip. A number of basic source-coupled FET logic (SCFL) digital cells (buffer, OR, XOR, AND, D-flip-flop) are simulated, as well as various ring oscillator configurations and a programmable 2/3 divider. The cells used to generate pulse signals from the sine generator and the output cells used for measurements are also characterized. The simulations show that operation up to 3-5 GHz may be achieved, which is consistent with what can be expected from the f/sub T/=20 GHz 0.5-/spl mu/m GaAs MESFET technology. The chip layout is being drawn and measurements were expected to be performed by the end of July 2002.