Control Flow Analysis for Bottom-up Portable Models Creation

Portable Test and Stimulus Standard (PSS) is a game-changing standard in the field of simulation-based verification. This paper focuses on creating a top-level PSS model of the Design Under Verification (DUV) using PSS models of its components (submodels). This is one of the most challenging problems the PSS is currently facing, and it is called vertical reuse of portable models. The hardest part is to create proper constraints for the interconnection of submodels to represent behaviour intended to be verified. This paper aims to evaluate a hypothesis that with the analysis of the control flow inside the DUV, it is possible to significantly simplify the reusability of PSS models in the vertical direction. The control flow analysis can provide valuable information for creating constraints, as the control signals influence the behaviour of the DUV the most. As the DUV, the execution stage subsystem of the PULP platform processor was selected, which is an open-source representative of the RISC-V processor subsystem. Firstly, PSS models for all components inside this subsystem have been created. Then, the control signals of all these components were traced, and a map of dependencies from the subsystem point of view was assembled. Afterwards, the analysis was used to create constraints for the component-level PSS models while interconnecting them into the top-level PSS model.