A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.