Quantum Transport Simulations of Sub-60-mV/Decade Switching of Silicon Cold Source Transistors

A steep-slope switch of silicon (Si) transistor with a “cold” source (CSFET) with a metal between p-type and n-type Si (pSi–M–nSi) is investigated by quantum transport simulations, which breaks the subthreshold swing (SS) limit by manipulating the density of states (DOS) of injected carriers. The injected current from the junction of pSi–gold (Au)–nSi is calculated to be over
$10^{{3}}~ {\mu } \text {A}/{\mu } \text {m}$
by first-principles quantum-transport simulations. Then, Si CSFETs are investigated and compared with conventional FETs and tunneling FETs. It is demonstrated that SS reaches 23 mV/decade in 15-nm Si CSFETs in the ballistic limit. ON-state current is as large as
${7}.{9} \times {10}^{{2}}\,\, {\mu } \text {A}/ {\mu } \text {m}$
at
${V}_{D} = {0}.{5} \text {V}$
with
${I}_{\text {off}}$
fixed at
$10~\text {pA}/ {\mu }\text {m}$
. The SS of CSFETs degrades with decreasing gate length and cannot be smaller than 60 mV/decade at
${L} _{G}$
= 6 nm. CSFETs have temperature-independent SS due to the cold electron injection, which is different from FETs and Dirac source FETs. The output characteristics demonstrate that CSFETs exhibit negative differential resistance and can achieve current rectification. Finally, the effects of cold electron rethermalization due to electron–phonon scattering in 15-nm CSFETs are found to degrade the SS to 50 mV/decade in six orders of magnitude of drain current. The SS can be improved to 42 mV/decade by using shorter lengths of the metal layer and n-type Si in the source to minimize the scattering.