Low Power and High Speed Comparator Design in Quantum-dot Cellular Automata

Quantum-dot Cellular Automata is a novel nanocomputing technology that allows the designing of extraordinarily low-power and highly dense circuits with very high operating frequencies. Digital comparators are utilized in many devices, including Central Processing Units, microcontrollers, servo motors and process controllers, to address data comparisons and other arithmetic operations. This work presents an energy-efficient and high-speed optimized QCA comparator design. The proposed comparator design utilizes two XOR gates with parallel input feed and two majority gates. The proposed design achieves considerable improvements in total energy dissipation, QCA cell count and latency compared to the preliminary designs. The results are also compared based on the Efficient Complexity Function, area usage and certain other metrics.