Optimizing Package Power Integrity: A Comparative Study of Multiple Techniques and Approaches

Package as the interconnect between the silicon die and board, we often observe voltage droop as the current flows from board VRM to the silicon die through the package power delivery network (PDN), coupling/crosstalk increase, and jitter increases with poor power routing and return path designs. These are the two major problems faced by the power integrity (PI) engineers when designing the package PDN and getting the best PI performance and cost-effective packages. In this paper, the authors will focus on these problems and propose several optimization techniques commonly used in package and board PDN design. The optimization techniques proposed in this paper were verified by Cadence PowerDC and XtractIM EDA tools.