Thin IC Chip Pickup Process Risk Analysis via Experiments in conjunction with Numerical Approach

In the semiconductor industry, bare die and wafer level chip scale packages (WLCSP) are particularly sensitive to stress during handling due to the lack of protection. A major challenge during the assembly process is the die pickup process for thin IC chips nowadays, which has become more critical with the industrial demand for high-performance chips that are thinner and larger form factor. To address this challenge, the paper identifies three key risks associated with the die pickup process, including die overstress leading to brittle crack, die stays on sawing tape after needle ejection event, die collides with its neighboring dies. In this paper, set of empirical tests have been carried out to evaluate the process parameter which includes die size, die thickness, needle pitch and the needle location shift. In parallel, finite element modeling with Fracture-Energy based debonding approach have been carried out to simulate and correlate the die pickup process event. Empirical testing in conjunction with numerical approach enables comprehensive risk analysis for die pickup process. The results show that die crack is particularly sensitive to the narrower needle pitch, thinner die thickness, while die collision with neighboring dies is more easily caused by thicker die, smaller die size, and larger needle location shift. Finally, the paper provides valuable guidance on optimization of product design and die-pickup process-setting to enhance the product reliability and manufacturing efficiency during the assembly process.