Flip Chip CSP Package Integrity and Reliability Evaluation

Over the past decade, flip-chip technology has revolutionized the way we think about semiconductor components and integrated circuits. This sophisticated manufacturing process enables high-performance and cost-effective products to be manufactured in smaller sizes. As well, there has been a significant focus on the development of Cu pillar bump interconnection in flip chip package since they feature higher I/Os with tighter pitches and better heat transfer. Moreover, the manufacturing cycle time and assembly cost could be decreased by using molded underfill (MUF) encapsulation instead of the combination of capillary underfill (CUF) and epoxy molding compound (EMC).In this paper, one Flip Chip CSP(FCCSP) package with Cu pillar bump and MUF process was developed. The wafer used is 14nm node wafer. Cu pillar bump is with 70um Sn-Ag cap and bump pitch is 141um. This paper listed detailed FCCSP package structure and process flow. Then it summarized evaluation results including ghost bump study, package integrity evaluation, package warpage performance check and reliability evaluation.The evaluation results concluded that this FCCSP package showed good extremely low-k (ELK) integrity and good package integrity. Package warpage can also meet JEDEC spec. As well, this FCCSP package showed no delamination issue after Moisture Level Sensitivity (MSL) 3, 260C preconditioning test and no package related fails up to 3X read point: 1056hrs HAST (Highly Accelerated Stress Test Highly Accelerated Stress Test) /2100 TC Temperature Cycle at temp (-55C~125C)/3000hrs HTSL ( High Temperature Storage Life ). It did show robust reliability performance for this FCCSP pkg.