Advancing Fine Pitch (< 5μm) Interconnects through Self-Aligned Die-to-Wafer Hybrid Bonding for Chiplet Integration

In the context of microelectronics, the ongoing trend of reducing interconnect pitch sizes to sub-micron levels presents a burgeoning challenge in die-to-wafer assembly. This challenge reverberates through various critical domains, including memory, logic, and the burgeoning landscapes of 5G and 6G applications. The pursuit of fine pitch integration underscores the paramount importance of achieving precise interconnect alignment. Our research is dedicated to the development of an industrial process capable of facilitating self-aligned assembly in the context of die-to-wafer bonding. Within this manuscript, we elucidate the integration approach made possible by this innovative assembly technique, accompanied by an in-depth exploration of our simulation work, which forecasts critical process parameters for achieving superior alignment accuracy post-placement.Furthermore, we validate the results of our simulations through meticulous experimentation, where we demonstrate alignment accuracy extending to an impressive 100 nanometres. This contribution, nestled within the context of die-to-wafer assembly, holds significance for a range of applications and industries, marking a substantial step towards addressing the challenges posed by shrinking interconnect pitch sizes.