The Effect of Cu/SiO2 Rough Interface on TSV Electroplating Process for Electronic Packaging

With the development of electronic device towards miniaturization, multi-function and high integration, the increasing power density brings more serious challenges to chip packaging. Through silicon via (TSV) is the most advanced 3D interconnection packaging technology because of the shortest distance and higher strength of vertical interconnects. However, different etching methods all will result in roughness on the sidewall of the through-hole, which significantly affects the reliability of the TSV-Cu electroplating process. Therefore, it is necessary to explore the influence of roughness on the TSV-Cu electroplating process. In this paper, the TSV-Cu electroplating models with different roughness sidewall were established via W-M fractal autocorrelation function. The electroplating of TSV-Cu was studied based on CuSO
4
electrolyte. The influence mechanism of different sidewall roughness on TSV-Cu electroplating was analyzed from the aspects of Cu
²⁺
ion distribution, potential distribution, current density, and coating thickness. The finite element results indicate that roughness can hinder the transportation of electrolytes, thereby slowing down the electroplating process, which deteriorates the reliability of TSV-Cu electroplating.