Demonstration and Challenges of Through Si Interposer (TSI) with 5-layer Frontside Cu Metal and 2-layer Backside Cu RDL

Through Silicon Interposer (TSI) is a promising technology to realize 2.5D/3D platform for high-performance computing like artificial intelligence (AI) and Internet of Things (IoT). There are needs to build more metallization layers on the frontside (> 3 layers) and backside (>1 layer) of TSI wafers for routing requirements. However, there are challenges in wafer level warpage control with increasing number of metal layers to be fabricated on the TSI wafers. This paper investigates the evolution of wafer warpage at different stages of the fabrication and solutions for the TSI process fabrication to realize on the frontside 5 metal layers using 1um Cu Dual Damascene (BEOL) and backside 2 layers of 3um Cu re-distribution layer (RDL). UBM process is implemented as the finishing layer on both frontside and backside of the TSI. In addition, the effect of the presence of TSV on wafer warpage in fabrication of the TSI will also be discussed.