Intra Die Super Power Pads Bonding for IR Voltage Drop Reduction in Automotive SoCs

With technology shrinking and increased integration with high performance leading to higher power consumption of the automotive integrated circuits SoCs. SoC designs with higher power consumption requires bigger packages such as flip-chip and wire-bond. Flip-chip package are more costlier than wire-bond packages but are better in terms of electrical performance (such as lower package resistance and inductance) w.r.t wire-bond packages to meet IR voltage drop requirement for SoCs. Though automotive SoCs are very sensitive to the overall cost and hence require low cost packages such as wire-bond packages and at the same time meet the power and IR voltage drop challenges. In wire-bond packages, as we know power is supplied from the power pads placed in the peripheral padring and hence causes maximum IR voltage drop in the center of the chip and least at the peripheral region of the chip. Here in this paper, we propose a novel method to place power pad over the die (named as Super Power Pad -SPP) based on the power distribution inside the chip to bring the power from the peripheral pads to different regions inside the chip to reduce IR voltage drop. Here in this proposed methodology these Super Power Pad placed at different region act like local voltage sources are bonded out to peripheral pads through intra-die bond wires to reduce the effective resistance from peripheral padring to internal region of the chip to reduce the overall IR voltage drop.