Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration

In our previous work, we discussed the demonstration of 10µm x 100µm Via-Last TSV (from top) fabrication on a blanket SOI Wafer, as illustrated in Fig 1(a) [1]. Analysis of the RF measured data on the mechanical test vehicle (MTV) wafers revealed that the TSVs' inductance and resistance were minimal and had a negligible impact on the RF performance [1]. This paper further investigates the process integration of Via-Last TSV (from top) fabrication on an actual low-noise-amplifier (LNA) device wafer. We observed the differences between the blanket SOI wafers and the LNA wafers in terms of incoming wafer surface topography and top oxide thickness uniformity. As a result, these differences pose a different set of process challenges in TSV formation on the frontside of the actual LNA device wafer as compared to a blanket SOI wafer. The step height at the pad area of the LNA wafers, measured by a laser microscope (Fig 2(c)), was approximately 1.3um. This topography could introduce potential residue defects, as depicted in Fig 3. Hence, additional process development is necessary to flatten the wafer surface to prevent the occurrence of any residue defects. Another process challenge faced by the actual LNA device wafer lies in the etching of the TSV. The total dielectric thickness of the LNA wafers is much higher than that of the dummy SOI wafers used in the previous study [1]. As such, achieving optimal TSV etching will require additional process tuning.